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[VHDL-FPGA-Verilog] 15AlteraIP

Description: 15个Altera的IP核，123456789101112131415-15AlteraIP
Platform: | Size: 47104 | Author: LaoY | Hits:

[Program doc] wp_wimax

Description: WiMAX, or the IEEE 802.16 standard for broadband wireless access, is increasingly gaining in popularity as a technology with significant market potential. This paper first provides an overview of the existing and developing 802.16 standards and their key differences/applications. The PHY and MAC layers of a typical WiMAX base station are then described. The associated implementation challenges faced by WiMAX infrastructure developers, including performance/cost/flexibility trade-offs in the choice of silicon, are clearly outlined. The paper then describes how FPGA-based system implementation can address these challenges including the “accelerated time-to-market” requirement which is considered a key enabler for early success in this market. As an example design, the physical layer implementation of the 802.16d standard with Altera FPGAs and intellectual property (IP) is proposed.
Platform: | Size: 473088 | Author: greg | Hits:

[Internet-Network] TCPIPGuide_2-0_s9

Description: WiMAX, or the IEEE 802.16 standard for broadband wireless access, is increasingly gaining in popularity as a technology with significant market potential. This paper first provides an overview of the existing and developing 802.16 standards and their key differences/applications. The PHY and MAC layers of a typical WiMAX base station are then described. The associated implementation challenges faced by WiMAX infrastructure developers, including performance/cost/flexibility trade-offs in the choice of silicon, are clearly outlined. The paper then describes how FPGA-based system implementation can address these challenges including the “accelerated time-to-market” requirement which is considered a key enabler for early success in this market. As an example design, the physical layer implementation of the 802.16d standard with Altera FPGAs and intellectual property (IP) is proposed.
Platform: | Size: 211968 | Author: greg | Hits:

[Software Engineering] ALTERA_PCI

Description: 关于ALTERA的PCI问答集Q1 What is PCI? What are the typical applications of a PCI bus? Q2 Who governs the PCI Specification? Q3 What level of participation does Altera have in developing PCI standards? Q4 What does the designer need to know about PCI to design with our IP core? -Q1 What is PCI? What are the typical applications of a PCI bus? Q2 Who governs the PCI Specification? Q3 What level of participation does Altera have in developing PCI standards? Q4 What does the designer need to know about PCI to design with our IP core?
Platform: | Size: 9216 | Author: bise | Hits:

[VHDL-FPGA-Verilog] crc_accelerator

Description: CRC 的Nios的软核处理，系统采用Altera Nios IP核进行CRC算法，算法运行时间比常规CRC校检节省很多。-CRC' s Nios soft-core processing, the system uses Altera Nios IP core for CRC algorithm, algorithm running time than the conventional CRC checkout save a lot.
Platform: | Size: 409600 | Author: lijiang | Hits:

[VHDL-FPGA-Verilog] altera_up_avalon_irda

Description: Altera大学计划的红外通讯IP，avalon接口-Altera University Program of the infrared communication IP, avalon interface
Platform: | Size: 485376 | Author: Royal Wang | Hits:

[Other Embeded program] SRAM_Controller

Description: altera 大学计划 程序包的sram controller ip-altera University Program package sram controller ip
Platform: | Size: 218112 | Author: suwen | Hits:

[VHDL-FPGA-Verilog] I2C_code

Description: 与IP核配套的I2C-Master Core，包含了目前主流FPGA芯片的I2C实现，代码包括Altera/Xilinx/OpenCore等公司的VHDL/Verilog/C等。-I2C-Master Core
Platform: | Size: 3256320 | Author: summerooooo | Hits:

[VHDL-FPGA-Verilog] RS232_NIOS_Verilog

Description: 5个文件，包含了RS232的nios实现和Verilog实现方式。其中,RS232的nios核实现只需要按照文件描述可以轻松实现^_^，个人比较推荐！RS232的Verilog实现需要编程，例程方便使用。RS232正在进一步学习中，有兴趣的可以探讨。-the realizition of rs232 interface by niosii uart ip core of Altera.it seems a most conveniet way.
Platform: | Size: 685056 | Author: summerooooo | Hits:

[SCM] AlterA8237IPcoreshost

Description: Altera公司可编程DMA控制器A8237的IP核host_dec模块-Altera, The Programmable DMA controller IP core host_dec module A8237
Platform: | Size: 3072 | Author: 张曼 | Hits:

[VHDL-FPGA-Verilog] ref-sqroot

Description: 求平方根的ip核，Altera提供，可以用在FPGA上，是AHDL语言写的，不开放源码-Square root of the ip seeking nuclear, Altera provides, can be used in FPGA, is written in AHDL, not open source
Platform: | Size: 39936 | Author: 张飞 | Hits:

[VHDL-FPGA-Verilog] Altera_Embedded_Peripherals_Handbook

Description: Altera公司原版资料，嵌入式设备handbook。-The handbook you are holding (the Altera Embedded Peripherals Handbook) describes Intellectual Property (IP) cores provided by Altera® for embedded systems design. The following is true of all cores described in this handbook:
Platform: | Size: 695296 | Author: Han Yunbo | Hits:

[VHDL-FPGA-Verilog] alteraipcore

Description: Altera公司的15个ip核的源代码，找了很久才找到的一些常用ip core-Altera 15 nuclear source ip
Platform: | Size: 999424 | Author: 李昀泽 | Hits:

[Embeded-SCM Develop] DM9000A

Description: altera的ip核，在sopcbuilder中添加后，在niosII IDE中可以轻易实现对dm9000a网卡的控制-The ip nuclear altera in sopcbuilder added after niosII IDE can be easily achieved in the control of dm9000a card
Platform: | Size: 16384 | Author: 張三 | Hits:

[VHDL-FPGA-Verilog] stratixIII_3sl150_dev_TSE_SGMII_v1

Description: 该程序实现altera开发板 stratix III 3S150通过以太网与pc之间通信。 使用Quartus II和Nios II 设计。 因为altera官方没有这块板子的正确网卡与pc通信的程序，-Overall This example works at 1000M/100M/10M Base SGMII mode on SIII 3S150 Kit. Designed by Quartus II/IP Cores/Nios II EDS v8.0 This is not an official released Design Example. It is only for your reference, but beyond the support area of ALTERA Mysupport.
Platform: | Size: 7244800 | Author: 杨庆育 | Hits:

[VHDL-FPGA-Verilog] altera_up_sd_card_avalon_interface

Description: altera公司面向大学的大学计划中sd的ip核源程序，-altera company plan for universities in the ip sd_card nuclear source,
Platform: | Size: 12288 | Author: 陈小林 | Hits:

[SCM] sd_card

Description: 面向altera公司的大学计划sd-card ip核，检测sd卡是否插入卡槽中。-Altera company s University Program for sd-card ip core, testing sd card is inserted into the card slot
Platform: | Size: 1643520 | Author: 陈小林 | Hits:

[VHDL-FPGA-Verilog] ALTERA_SRAM_IP

Description: ALTERA公司的SRAM IP核，加快设计流程-ALTERA company SRAM IP cores, speeding up the design process
Platform: | Size: 146432 | Author: sqf | Hits:

[VHDL-FPGA-Verilog] source

Description: SDRAM控制器源代码，是ALTERA公司的IP源核，很好很强大-SDRAM controller source code, very very strong
Platform: | Size: 11264 | Author: 张理 | Hits:

[VHDL-FPGA-Verilog] ModelSim_ALTERA_

Description: 介绍了采用modelsim仿真altera器件IP Core时如何添加altera的仿真库方法，中文版。-This article describes how to add simulation library to simulate altera，s IP Cores by Medelsim。
Platform: | Size: 214016 | Author: lh | Hits:
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